A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of wiring metal strips. In VLSI chips, these metal patterns are multilayered and separated by layers of an insulating material. Interconnections between different metal wiring patterns are made by holes (or via holes), which are etched through the layers of insulating material. Typical chip designs consist of one or two wiring levels, with three wiring levels being the current state of the art. Circuit cost and performance continue to place demand on the fabrication processes in such a way that adding supplementary wiring levels can be competitive even though additional processing steps are required. However, the technique using via-holes, although widely used today, has multiple limitations and drawbacks in that, as the number of metallization layers increases wiring becomes increasingly difficult.
One particular drawback is that the structure produced leads to a very irregular surface, far from planar. Since it is necessary that the structure be planar, the surface is made planar by a variety of planarizing techniques.
It is well known to use ceramic substrates, particularly multilayer ceramic (MLC) substrates, as supports for mounting semiconductor devices thereon.
MLC technology for producing substrates for integrated circuit semiconductor package assemblies is well known in the art. The resultant substrate is capable of mounting many devices which are interconnected by the internal circuitry. External contact is made by a plurality of input/output (I/O) pins on the bottom side. The substrate is provided on the top surface with many small pads which are suitable for making solder connections to corresponding device terminals. Such MLC substrates require a relatively complex metallurgy on the topside to make connections to the integrated circuit devices and provide engineering change pads, and on the bottom to make connection to the I/O pads or other type connections. The complex metallurgy is comprised of several layers of metal which are selectively deposited in a predetermined pattern by additive and/or subtractive photolithographic processes.
Prior to the deposition of the top and bottom surface metallurgy, it may be desirable to planarize the surface of the substrate. The planarization may be accomplished by a variety of planarization techniques.
Instead of placing the top and bottom surface metallurgy directly on the surface of the ceramic substrate, the metallurgy may be placed on an intervening thin film layer (or a plurality of thin film layers) such as that disclosed in Boss et al. U.S. patent application Ser. No. 167,290, filed Mar. 11, 1988, the disclosure of which is incorporated by reference herein.
Again, prior to the deposition of the top and bottom surface metallurgy, it may be desirable to planarize the thin film layer. The planarization may be accomplished by a variety of planarization techniques.
Of the planarization techniques available today, a preferred one for electronic component substrates is chemical-mechanical (hereinafter chem-mech) polishing such as that disclosed in Chow et al. U.S. Pat. No. 4,702,792 and Beyer et al. U.S. patent application Ser. No. 791,860, filed Oct. 28, 1985, the disclosures of which are incorporated by reference herein. Also of interest is Rea U.S. Pat. No. 4,475,981, the disclosure of which is also incorporated by reference herein. Chem-mech polishing essentially enhances the removal of surface material by mechanically abrading the surface while applying an etchant that chemically attacks the surface. In order for chem-mech polishing to work, there must be at least two materials having differing etch rates such that the etchant affects one material more than the other. The effectiveness of the chem-mech polishing method ultimately depends on the precise etchant chosen.
For one reason or another, the chem-mech polishing slurries of the prior art have failed to produce a substrate surface that is acceptably planar.
Accordingly, it is an object of the present invention to have an improved chem-mech polishing method and slurry.
It is another object of the present invention to have an improved chem-mech polishing method and slurry that is available for use on a plurality of different material combinations.
These and other objects of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.